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2019-01-23 - Article/Compte-rendu - Anglais - page(s)

BLAIECH Ahmed Ghazi, BEN KHALIFA Khaled, Valderrama Carlos , FERNANDES Marcelo A.C., BEDOUI Mohamed Hedi, "Taxonomy of FPGA-Based Topologies for Future Deep Learning Architectures" in Journal of Systems Architecture

  • Edition : Elsevier (Netherlands)
  • Codes CREF : Sciences de l'ingénieur (DI2000), Techniques d'imagerie et traitement d'images (DI2770), Technologies de l'information et de la communication (TIC) (DI4730), Semi-conducteurs (DI2512), Electronique et électrotechnique (DI2411), Instrumentation médicale (DI2760), Conception assistée par ordinateur (DI1247), Electronique générale (DI2510), Electricité (DI1230)
  • Unités de recherche UMONS : Electronique et Microélectronique (F109)
  • Instituts UMONS : Institut de Recherche en Technologies de l’Information et Sciences de l’Informatique (InforTech), Institut NUMEDIART pour les Technologies des Arts Numériques (Numédiart)
  • Centres UMONS : Centre de Recherche en Technologie de l’Information (CRTI)
Texte intégral :

Abstract(s) :

(Anglais) Deep learning, the fastest growing segment of Artificial Neural Network (ANN), has led to the emergence of many machine learning applications and their implementation across multiple platforms such as CPUs, GPUs and reconfigurable hardware (Field-Programmable Gate Arrays or FPGAs). However, inspired by the structure and function of ANNs, large-scale deep learning topologies require a considerable amount of parallel processing, memory resources, high throughput and significant processing power. Consequently, in the context of real time hardware systems, it is crucial to find the right trade-off between performance, energy efficiency, fast development, and cost. Although limited in size and resources, several approaches have showed that FPGAs provide a good starting point for the development of future deep learning implementation architectures. Through this paper, we briefly review recent work related to the implementation of deep learning algorithms in FPGAs. We will analyze and compare the design requirements and features of existing topologies to finally propose development strategies and implementation architectures for better use of FPGA-based deep learning topologies. In this context, we will examine the frameworks used in these studies, which will allow testing a lot of topologies to finally arrive at the best implementation alternatives in terms of performance and energy efficiency. Keywords: Deep Learning, Framework, Optimized implementation, FPGA.

Identifiants :
  • DOI : https://doi.org/10.1016/j.sysarc.2019.01.007