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2014-02-25 - Colloque/Article dans les actes avec comité de lecture - Anglais - 4 page(s)

Tarrillo Jimmy, Escobar Juzga Fernando, Lima Kastensmidth Fernanda, Valderrama Carlos , "Dynamic Partial Reconfiguration Manager" in IEEE LASCAS Latin American Symposium on Circuits and Systems, Santiago, Chile, 2014

  • Codes CREF : Systèmes experts (DI1181), Electronique et électrotechnique (DI2411)
  • Unités de recherche UMONS : Electronique et Microélectronique (F109)
  • Instituts UMONS : Institut de Recherche en Technologies de l’Information et Sciences de l’Informatique (InforTech)

Abstract(s) :

(Anglais) Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.

Identifiants :
  • DOI : 10.1109/LASCAS.2014.6820293