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2017-01-02 - Article/Dans un journal avec peer-review - Anglais - 5 page(s)

M. Avelino Álvaro, O. Roda Valentin, Valderrama Carlos , Alves De Albuquerque Glauberto Leilson , DA CUNHA POSSA P., "Partial Reconfiguration Exploration Over P2IP Architecture" in Przeglad Elektrotechniczny, 2017, 1, 258-262, doi:10.15199/48.2017.01.63

  • Codes CREF : Sciences de l'ingénieur (DI2000), Technol. des composantes électroniques [microélectronique] (DI2521), Electronique et électrotechnique (DI2411), Electricité (DI1230)
  • Instituts UMONS : Institut de Recherche en Technologies de l’Information et Sciences de l’Informatique (InforTech), Institut NUMEDIART pour les Technologies des Arts Numériques (Numédiart)

Abstract(s) :

(Anglais) P2IP is a real-time image and video processing architecture featuring reconfigurable runtime capabilities, low latency and high performance. However, low energy consumption and battery life are crucial when targeting portable devices. In some applications, not all processing elements are in use representing a power leak that a Partial Reconfiguration (PR) strategy could mitigate. To assess its impact, three image processing algorithms have been deployed in a variant of this architecture implemented in an FPGA. Measurements show that use of PR leads to energy savings of up to 45%.